The present invention relates to a microcomputer applied control unit for use in a motor vehicle.
FIG. 1 shows a general configuration of a conventional microcomputer, which comprises a Read Only Memory (ROM) 1 in which instruction codes and data are stored, a Central Processing Unit (CPU) 2 for sequentially processing the instructions stored in the ROM 1, an I/O (Input/Output) port 3 for inputting digital data 104 and outputting a signal to a controlled system 105, a Data Direction Register (DDR) 4 for setting the input/output direction of the I/O port 3, a Random Access Memory (RAM) 5 to or from which the CPU 2 is capable of writing or reading data, a stack pointer 6, and a programmable timer 7.
The CPU 2, ROM 1, I/O port 3, DDR 4, RAM 5 stack pointer 6 and programmable timer 7 are adapted to receive and give data with one another. The I/O port 3 outputs data to the controlled system 105.
Generally, the input/output direction of the I/O port 3 is set once in an initial setting step if the input/output direction should not be changed, as described in the Integrated Circuit Catalog of Fujitsu, Ltd. No. GD-001050-2C, p. 213.
A description will be given to instruction programs stored in the ROM 1. FIG. 2 shows an essential flowchart of the executive routine of a conventional control program. According to the control program shown in FIG. 2, the stack pointer 6 and the programmable timer 7, for example, together with the DDR 4 are initially set at a STEP 31.
At STEP 32 where input data is needed, the input data is directly read from the I/O port 3 and utilized for operational processing at STEP 33.
At STEP 34 where input data is again needed, the input data is again read from the I/O port 3 and utilized for operational processing in STEP 35, in the same manner practiced in STEP 32.
In the afore-mentioned system of the conventional control program execution, the DDR 4 is set up once in the initial setting STEP 31 and not reset during the postprocessing.
In that case, the contents of the DDR 4 may alter for some reason, e.g., noise, and the input/output direction of the I/O port 3 may also change when the contents of the DDR 4 are altered after the initial setting is completed at STEP 31 in the processing routine. Therefore, such a system is disadvantageous in that the digital data 104 cannot be read accurately.